Interpolation pulse duration modulated adder

ABSTRACT

A pulse duration modulated (PDM) signal is generated from a periodic digitized signal which may be produced by sampling an analog signal of frequency F s  and using a digitizing frequency F where F&gt;&gt;F s . Linearity of the analog signal between sampling points is assumed. A computer solution of the intercept of the assumed straight line between each pair of successive sample values of the digitized signal and a reference triangular waveform of frequency F/2 provides the time interval between intercepts from which the interpolated pulse duration modulated (IPDM) waveform is generated. A method to add low frequency signals in the IPDM domain, useful for providing Class AD amplifiers with a feedback path and for summations of input signals without converting signals back to analog form, operates on the sum of the respective intercept times of each of the signals. The summed intercept times are used to provide an IPDM signal which represents the sum of the original digitized signals. Multiplication of digitized signals in the nonlinear (IPDM) domain is provided by operating on the product of the intercepts of two IPDM signals to obtain the intercepts of a new IPDM signal whose low frequency content is the product of the low frequency component of the two digitized signals. Interpolated signals thus are able to be modulated and frequency shifted in the IPDM domain to improve the linearity of IPDM for higher frequency signals (F not much greater than F s ).

BACKGROUND OF THE INVENTION

This invention relates to pulse duration modulation and, moreparticularly, to a method and apparatus for providing a pulse durationmodulation signal by using digital techniques useful for transmittersoperating in a switched mode.

Pulse duration modulation (PDM) codes a relatively low frequency signalinto a two-state waveform. Advantages exist in using this binary(two-state) time series. One consequence is that an amplifier thatprocesses the coded waveform operates in a "switch" (Class D) modeinstead of a "linear" mode (Class A or B). In other words, Class Damplifiers respond to PDM commands to turn solid state devices either"ON" or "OFF" in proper sequence. The output stage of the powertransmitter, controlled in such a manner, amplifies the two-statewaveform.

An important characteristic of the subsequent high power output signalis its low frequency content. If the PDM output is low-pass filtered,low frequency spectral components track linearly with the original lowfrequency input over a broad dynamic range. The input signal (the lowfrequency signal) is modulated by a high frequency carrier in thepulsewidths of the switch mode wave.

Several methods of generating a pulse duration modulated signal areavailable. A PDM waveform can be formed in both an analog or digitalway. Digital processing is advantageous for several reasons. Firstly, ifthe input waveform is already in a digital format, digital-to-analogconversion is not required. Another important factor is that reliabilityincreases by using a digital approach, since problems inherent to analogcircuits do not exist in digital hardware. In the digital domain,however, other factors must be considered if a truly analogous approachto analog PDM is taken.

A prior art analog (continuous time) circuit 10 for generating a pulseduration modulated signal is shown in FIG. 1. X(t) and D(t) are bothcontinuous waveforms. X(t) is the low frequency input signal. D(t) is arelatively high frequency triangle signal which will be referred to as adither waveform. The amplitudes of the two signals are compared by alinear comparator 11 to provide E(t) which, in turn, drives a two statedevice 12 such as a relay whose output terminal is alternately connectedto voltage sources +G, -G to provide an output signal Y(t). If X(t) isgreater than D(t), Y(t) having a level +G is generated at the relay'soutput. The opposite output level, -G, is produced if X(t) is less thanD(t).

Analog circuitry has inherent problems that are difficult, if notimpossible, to overcome. Components must be properly calibrated tocompensate for hardware tolerances and drift. For these reasons,processing inaccuracies are induced due to physical device limitations.Circuit input must also be considered. A digital input to an analog PDMsystem requires D/A conversion of the signal prior to modulation toproduce the binary output waveform. The additional hardware complexityin the D/A conversion process may reduce system reliability.

An analogous pulse duration modulator can be built in the digitaldomain. An approach to this circuit design is to compare,simultaneously, at a fixed rate, samples of a digital input signal X(nt)with coincident samples of a digital triangular wave D(nt). A very highinput data rate is needed to compare X(nt) and D(nt) to obtainappropriate PDM waveform definition. As a consequence, high speeddigital hardware is required to compare the two signals and tosufficiently define the PDM waveform. Hardware presently is notavailable to construct an analogous digital amplifier that will meetneeded output requirements.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide a pulse durationmodulation transmitter which has an output which is stable, convenientto utilize with digital input signals, and whose output is a linearfunction of its input with distortion within specified requirements.

It is a feature of this invention that the pulse duration modulation isproduced by interpolation of the sampled input signal to determine itscrossover points with a reference (dither) signal from which crossoverpoints the pulse duration is obtained.

The invention produces a time duration modulated signal from a sequenceof digital input signals representing the sampled amplitudes of ananalog signal sampled at a frequency F. The sampling frequency F is manytimes larger than the highest frequency of the analog signal so that thesignal is assumed linear between each pair of sampled values. Theinterpolated intercepts of the linear signal with a triangular waveformof frequency F/2 whose apices are time coincident with the signalsamples provide the times at which the output waveform changes state tothereby produce the interpolated pulse duration modulated (IPDM) signalin which the input signal is encoded.

A computer solution of the intercept of the assumed straight linebetween each pair of successive sample values of the digitized signaland a reference triangular waveform of frequency F/2 provides the timeinterval between intercepts from which the interpolated pulse durationmodulated (IPDM) waveform is generated. A method to add low frequencysignals in the IPDM domain, useful for providing Class AD amplifierswith a feedback path and for summations of input signals withoutconverting signals back to analog form, operates on the sum of therespective intercept times of each of the signals. The summed intercepttimes are used to provide an IPDM signal which represents the sum of theoriginal digitized signals. Multiplication of digitized signals in thenonlinear (IPDM) domain is provided by operating on the product of theintercepts of two IPDM signals to obtain the intercepts of a new IPDMsignal whose low frequency content is the product of the low frequencycomponent of the two digitized signals. Interpolated signals thus areable to be modulated and frequency shifted in the IPDM domain to improvethe linearity of IPDM for higher frequency signals (F not much greaterthan F_(s)).

It is a further object of the invention to provide a method for addingIPDM signals, useful for providing Class AD amplifiers with a feedbackpath and for summations of input signals without converting signals backto analog form, by summing the intercept times of each of the IPDMsignals. The summed intercept times are used to provide a IPDM signalwhich represents the summed signals.

It is still a further object of the invention to provide amultiplication of signals in the nonlinear (PDM) domain by themultiplication of the intercepts of two IPDM signals to obtain theintercepts of a new IPDM signal whose low frequency content is theproduct of the low frequency component of the two signals. Interpolatedsignals by this procedure are able to be modulated and frequency shiftedto improve the linearity of IPDM for higher frequency signals.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned aspects and other features of the invention areexplained in the following description taken in conjunction with theaccompanying drawings wherein:

FIG. 1 is a block diagram of a prior-art pulse duration modulationcircuit;

FIG. 2 shows waveforms illustrating conceptually the sampling of asignal and its intersection with a dither signal to produce a pulseduration modulated signal;

FIG. 3 is a block diagram of a circuit providing an interpolated pulseduration modulated signal by computation of intercept time of signal anddither signals;

FIG. 4 is a block diagram of a circuit using a one-term Maclaurinexpansion approximation of the intercept time of signal and dithersignals;

FIG. 5 is a block diagram of a circuit using a two-term Maclaurinexpansion approximation of the intercept time of signal and dithersignals;

FIG. 6 is a block diagram of a negative feedback amplifier of the priorart for a pulse duration modulated signal;

FIG. 7 is a block diagram of a negative feedback amplifier usinginterpolated pulse width modulation signals;

FIGS. 8a, 8b, 8c and 8d are waveforms illustrating the addition ofinterpolated pulse width modulation signals;

FIG. 9 is a block diagram of a circuit for adding interpolated pulseduration signals;

FIG. 10 is a block diagram of a circuit for adding one or two-termapproximation interpolated pulse duration signals;

FIGS. 11A and 11B are waveforms illustrating multiplication ofinterpolated pulse duration signals; and

FIGS. 12 and 13 are block diagram circuits for multiplication of linearinterpolated and approximation interpolated pulse duration signals,respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENT Interpolation Pulse DurationModulation (IPDM)

This invention provides a considerably more effective digital approachto PDM generation. This method utilizes characteristics of the inputsignals (the triangular and sinusoidal waveforms) and the output twostate waveform (the PDM waveform). A characteristic property of theinputs to the modulator (the low frequency input signal X(t) and thehigh frequency dither signal D(t)) is that the triangle dither waveformis at a frequency much greater than the input sinusoid (F>>F_(s)). InFIG. 2, the system inputs X(t), D(t) and the PDM output Y(t) are shown,Y(t) being assigned the value +G for time instances at which X(t)>D(t)and the value -G when X(t)<D(t).

From FIG. 2 it is seen that to generate the PDM signal Y(t) onlyknowledge of the instances at which the input sinusoid X(t) crosses thedither signal D(t) and the slope of the dither signal at the crossovertimes are needed to define the two state waveform Y(t). The crossoverpoints define the switch times of the two state waveform. Addedinformation related to one slope of the dither signal is used to definethe actual state at the two state switch (whether +G or -G). A change inoutput state is thus defined from the crossover time and the dithersignal slope. Particularly, at a crossover time, if the slope of D(t) isnegative, state Y(t) is positive until the next switch point. On theother hand, Y(t) is negative until the next switch point if the slope ofD(t) is positive at the crossover time. Information at times other thanat the crossovers is superfluous because the output state of Y(t)remains constant between crossovers. Consequently, if the switch pointsand respective dither signal slopes are known, no further information isrequired to define the two state output waveform Y(t).

Reference to FIG. 2 illustrates that the triangular dither signal D(t)is linear, with constant slope over one-half the dither period. Thedither signal is still linear over the second half of the dither period;however, the sign of its slope has reversed. The sinusoidal input signalX(t), also, since its frequency is considerably less than that of thetriangle waveform, can be considered to be piecewise linear betweenadjacent sampled values 20. These sampled values of the input signaloccur at the time the waveform D(t) is at its peak extremities whichhappens every one-half dither period (T/2).

The dither signal is defined in a.piecewise sense within 1/2 a ditherperiod by the equation:

    D(t)=m't+b'                                                (1)

where

m'=÷4A/T and b'=∓A;

A=the magnitude of the peak dither signal amplitude which alternatessign every T/2 sec; and

T=the period of the dither signal.

The input signal is piecewise defined within 1/2 the dither period as:

    X(t)=mt+b                                                  (2)

where m=[2/T][X(nT/2)-X((n-1)T/2)] and b=X[(n-1)T/2] where n is thedither signal 1/2 period number (n=0, . . . , k).

The output waveform Y(t) changes state when:

    X(t)=D(t).                                                 (3)

The output state change within 1/2 a dither period (T) is defined as:

    Y(t)=+G when sgn [m']=-1 for (n-1)T/2<t≦nT/2;

    Y(t)=-G when sgn [m']=+1 for (n-1)T/2<t≦nT/2.

The intercept time, τ, referenced to the sample instant at the beginningof each half period (T/2) of the dither signal D(t), is easily computedby solving the intercept equation, Equation 3, for the variable, τ(where τ is measured from the apex of the dither signal). In particular,

    τ=(b'-b)/(m-m').                                       (4)

The process to determine the intercept time is repeated for allintervals spaced T/2 apart. Samples of the input and dither signals areneeded to solve for τ; but only those successive samples spaced T/2seconds apart are used for each successive computation of τ. In contrastto the prior art digital PDM processing method discussed earlier, thisapproach greatly reduces the input sampling rate. An additional featureof interpolation PDM method is that the dither signal D(t) is notphysically generated. Pairs of constants ([-b', +m'], [+b', -m']) whichalternate at a T/2 rate, define the triangular waveform and are insertedin the intercept time equation (4). As a result, a pseudo-dither signalis constructed using the appropriate pair of constants. The additionalvariables b and m are derived from successive samples of the inputsignal spaced T/2 sec. apart.

The interpolation process just described is implemented by the IPDMmodulator 30 shown in the diagram of FIG. 3. The IPDM output signal Y(t)is generated by sampling a low frequency input signal X(t) every T/2sec. in sample circuit 31. The sampled signal 32 is held for T/2 sec. inhold circuit 33 at which time it is available as a signal at the output34. The delayed signal at output 34 and the undelayed sampled signal atterminal 32 are provided to arithmetic processor 380 which computes theslope m (for equation 4) from these values of X(t). The value of thedelayed signal at output 34 is the value b for Equation (4). Thearithmetic processor 380 has another input from registers 36 whichalternates at the rate T/2 and provides the input pairs [m'=+2A, b'=-A]and [m'=-2A, b'=+A], respectively, at its outputs 37 and 42. The inputsto arithmetic processor 380 are used in the computation of the intercepttime τ (equation 4). A count, N, at the rate F' of the time τ isprovided every T/2 seconds at output 38 of IPDM processor 35. The countN of the computed values of τ are provided to a counter 39 that operatesat a frequency F' providing a pulse at its output 400 τ+ε sec. after thesync pulse (frequency 2F). The sync pulse occurs every T/2 sec. ε is atime error due to finite pulse time resolution. The output 400 pulseactuates a two-state switch 41 which has another input 421 which carriesthe sign information of the slope m' to define the polarity of theoutput Y(t). If m' is positive, the output Y(t) of switch 41 is -G,whereas if m' is negative, Y(t) is +G. Switch 41 includes a Class ADamplifier (not shown) which provides the gain factor G foramplification.

A time delay of T/2 seconds exists between the intercept time of inputX(t) and the time of change of state of output Y(t) if the time tocompute the intercept is assumed to be negligible. A maximum time delayof T/2 is permitted to generate the IPDM signal in real time with thestoring of only one input sample. An additional group delay (phaseshift) is added if computation time is considered.

The components of modulator 30 are easily implemented by digitalhardware. The most difficult operation in the overall process is thecomputation of the intercept time in real time. The maximum time allowedto calculate the intercept is limited to T/2 sec. Different algorithmicapproximations of the switch time are possible that allow thecomputation to be made in the time available with standard digitaldevices.

A procedure to approximate the intercept time is to substitute a powerseries, or Maclaurin series, expansion for the exact analyticalexpression of Equation 4. The solution to the time of intercept, τ, maybe approximated by a two-term Maclaurin expansion, given byf(x)=f(0)+(x)(f'(0)), where, f'(0)=the first derivative of the exactintercept expression. A one-term Maclaurin expansion is simpler and isof the form f(x)=f(0). Both one-term and two-term expansions areimplemented to validate the performance of the IPDM Class AD amplifier.The power series approximations reduce a time-consuming division ofEquation (4) to a set of multiplications. Even though seriesapproximations to the IPDM intercept time are made, sufficient accuracyis maintained in describing the intercept time.

Another consideration that affects amplifier performance is word length.The accuracy of mathematical operations is a function of the number ofbits required to sufficiently represent the data. Computational errors,together with inaccuracies dependent upon how well the input samples andoutput switch times are defined must be considered to appropriatelypredict performance and to physically validate system operation.

A list of system performance and hardware constraints are summarized inTable 1. These specifications are incorporated in the design of an IPDMmodulator. Two modulator configurations are considered. One of them,IPDM modulator 40 shown in FIG. 4, embodies the processes depicted inFIG. 3 but utilizes a one-term Maclaurin expansion in the IPDM processor35'. The other modulator 50 of FIG. 5 uses a two-term approximation. Theone-term expansion amplifier 40 is based on computing the intercept timeby the following Maclaurin approximation to the true intercept time.

    τ.sup.one term =[T/2][(X(n-1)T/2) ±A)/±2A]       (5)

Reference to the waveforms X(t), D(t) on FIG. 4 and Equation 5 showsthat the true intercept time .sup.τ true of X(t) with D(t) differsslightly from the approximate intercept time, τ_(one-term), obtainedfrom Equation 5. It is observed that the time intercept .sup.τ one-termof the one-term Maclaurin approximation is obtained from the interceptof D(t) with X(t) at the time (n-1)T/2. X(t) is considered to have zeroslope (to be constant) over the complete T/2 interval.

    τ.sub.two-term =[T/2][X(n-1)T/2) ±A][[(1/(±2A)]-[(X(nT/2) -X((n-1)T/2))/(2A)]].                                     (6)

Reference to waveforms X(t), D(t) of FIG. 5 and Eq. (6) show that thetime intercept .sup.τ two-term is obtained by estimating with a two-termexpansion the intersection of the waveform D(t) with straight line 51,having a value X[(n-1)T/2] at time [(n-1)T/2] and having a slope[X(nT/2)-X[(n-1)T/2]]/(T/2).

                  TABLE 1                                                         ______________________________________                                        IPDM AMPLIFIER SYSTEM PARAMETERS                                              ______________________________________                                        Output Clock Frequency (F')                                                                         17.92  mHz                                              Output Clock Period (T')                                                                            5.58   10.sup.-8 sec.                                   Input Signal Frequency (F.sub.S)                                                                    2      kHz to 4 kHz                                     Dither Signal Frequency (F)                                                                         35     kHz                                              Dither Period (T)     2.86   10.sup.-5 sec.                                   Input Word Length     11     Bits + Sign                                      Dither Signal Peak Amplitude (A)                                                                    1      volt                                             ______________________________________                                    

The input word length of the sampled signal X(nT/2) is limited in thedesigns of FIGS. 4 and 5 to 12 bits (11 bits +1 sign bit). Fixed pointarithmetic is also assumed. From the sampled input and the pseudo dithersignal (D(t) sample value of +1, -1 at intervals of T/2), the number ofclock counts necessary to generate the appropriate switch times(relative to a clock sync pulse each T/2 sec.) is computed. Each clockcount represents discrete time units of T' seconds. With thespecifications listed in Table 1, the clock count N, which the IPDMprocessor 35 and counter 39 must have the capacity for handling, for aone-term expansion is:

    N.sub.one term =[2.sup.-4 ][X((n-1)T/2) ±2047].

A two-term configuration necessitates additional processing complexity.For this case, the clock count N which must be handled by processor 35and counter 39 is determined by computing:

    N.sub.two term =[2.sup.-16 ]·[±4094-(X(nT/2)-X((n-1)T/2))]·[±2047 +X((n-1)T/2)].

The IPDM processor 35' of amplifier 40 of FIG. 4, which implements Eq.5, has a memory 46 which stores the peak value A of the dither signalD(t) as an eleven bit binary number (2047 decimal) and a sign bit. Themaximum binary representation of the input signal X(t) is limited to thesame number of bits. The input signal X(t) is sampled in sample and holdcircuit 31 by the sync pulse 2F of generator 56 to provide the samplevalues X(nT/2). The sampled input signal X(nT/2) has its signeffectively alternated every T/2 seconds by the sync pulse 2F from thesync pulse generator 56 applied to switch 42 whose arm 422 makesalternate connections to the + and - inputs of summing circuit 43. Theoutput of switch 42 and memory 46 are summed in digital summing circuit43 which provides a sign plus twelve bit output. The sign plus the eightmost significant bits of the output of summing circuit 43 are extractedfrom the 13 bit-input register 44. The output of register 44 is gatedinto counter 39 every T/2 seconds by the sync pulse 2F of generator 56.The counter is reinitialized each time it is gated. Counter 39 isclocked by clock pulse source 391 at frequency F'=17.92 mHz and providesa trigger pulse at its output line 392 when the count provided byregister 44 is reached. The trigger pulse 392 switches the output stateof Y(t) of the two-state switch 41. In order to preserve the phase ofX(t) in the PDM signal Y(t), the signal on line 421 indicating theposition of switch arm 422 of switch 42 is provided to two-state switch41 so that the output state of Y(t) is +G when the arm 422 is connectedto the positive input of the summer 43 and Y(t) is -G when arm 422 isconnected to the negative input of the summer 43.

The signal processing for the two-term expansion approximation of X(t)is provided by the IPDM.processor 35" of amplifier 50 of FIG. 5 whichimplements Equation (6). The input signal X(t), which is a digitalsignal whose binary representation cannot exceed eleven bits plus a signbit (-2047<X(t)<+2047), is sampled by sampler 31 at the sync rate 2F(T/2 seconds) provided by sync circuit 56. The output of sampler 31,(X(nT)), is provided to a delay circuit 52 of delay T/2 seconds and alsoto a subtract input of summer 53. The output X[(n-1)T/2] of delay 52 attime nT/2 is provided to a positive input of summer 53. A twelve bitbinary number and sign bit (+4094 or -4094) is alternately provided by aswitched register 51, which is switched at the sync rate 2F, to apositive input of summer 53. The output of summer 53 is provided as a 13bit binary number and a sign bit to multiplier 54. The output of summer53 implements the third bracketed term [] of Equation (6).

A register 55 whose output is switched at the sync rate 2F (T/2 sec.)provides an eleven bit binary number and a sign bit (+2047 or -2047 inaccordance with the positive or negative polarity, respectively, of thesignal on line 421) to a summer 57. The other input to the summer 57 isthe delayed signal X[(n-1)T/2] provided at the output of delay 52. Theoutput of summer 57 implements the second bracketed [] term of Equation(6) and is defined by a twelve bit number and a sign bit.

The outputs of summers 53, 57 are provided as inputs to multiplier 54whose output is defined by a twenty-five bit number and a sign bit whichis provided to a register 58 where only the second through ninth mostsignificant bits (a binary number representing a maximum decimalequivalent of 256) of the multiplier 54 output are retained. The syncpulse circuit 56 gates the output of register 55 into counter 39 at a 2Frate. The counter is reinitialized for each sync pulse. Counter 39 isclocked at the frequency F' (17.92 MHz) and provides an output pulse online 392 when the count is reached. The count will be reached within thetime T/2 so that the counter 39 is ready to receive a new number at the2F rate from register 58 at the next sync pulse. The pulse on line 392causes the output state Y(t) of the two-state switch 41 to change to theopposite state. In order to preserve the phase of X(t) in the PDM signalY(t), the sign information at switched register 51 is provided by thesignal on line 421 to switch 41 (also to switched register 55) so thatthe output state of Y(t) is +G when the arm 422 of register 51 isconnected to positive 2A and Y(t) is -G when the arm 422 is connected tonegative 2A.

In both FIGS. 4 and 5, bits in excess of those needed by the counter 39are discarded. The second through ninth bits of multiplier 54 of FIG. 5are used to compensate for a scale change made in the implementation ofequation 6 by amplifier 50. It should also be noted that the maximumvalue of X(t) is not allowed to exceed the value of A. The output Y(t)of the amplifier 50, when lowpass filtered, (i.e., applying Y(t ) to afilter that allows.passage of the highest frequency F_(s) in inputsignal X(t)) retains the amplitude tracking and phase characteristics ofthe original input sinusoid. The peak amplitude of this filtered signalis scaled by the factor G.

IPDM WAVEFORM ADDITION

The prior art Class AD amplifier design 70 shown in block diagram formin FIG. 6, utilizes an analog feedback control method to meet systemperformance criteria. Analog control signals 71 monitoring the pulsewidth modulator 74 and amplifier 75 functions are linearly summed(negative feedback) in an analog manner in adder 72 to the low frequencyanalog input signal 73. The resulting analog waveform is pulse durationmodulated (PDM) in a conventional modulator 74 and amplified by theClass AD amplifier 75 to provide a digital PDM output 77. The circuit 70of FIG. 6 requires the use of an analog feedback control network 76 forcompensation.

IPDM digital feedback, on the other hand, is feasible if the input 81and the feedback signal 89 are combined after they are individuallyprocessed by IPDM processors 35. To achieve linear feedback outputquantities on lines 85, 82, respectively, as shown in the circuit 80 ofFIG. 7, must be summed in the IPDM domain by IPDM adder 86. The summingof IPDM signals 82, 85 in IPDM adder 86 should effectively performlinear addition in the IPDM domain before signal 88 is applied as aninput.signal to amplifier 87. The IPDM addition process allows thecombination of two-state signals in the nonlinear IPDM domain instead ofin the linear time domain to obtain a new IPDM signal with the desiredlinear waveform characteristics. The low frequency content of theresulting IPDM signal on line 88 contains the linear sum of the lowfrequency components contained in the original IPDM inputs 82, 85.Negative feedback is accomplished by a 180° phase shift of filteredfeedback signal 89 represented by the negative sign 841 at the input ofits processor 35. The Class AD amplifier 87 is explicitly shown eventhough it is implicitly a part of two-state switch 41 having a gain G inIPDM adder 86 both shown in FIG. 9.

The process of combining two PDM waveforms and retrieving the linear sumof their respective low frequency components evolves from the lowfrequency analysis of a single two-state waveform.

Principles extracted from the IPDM procedure of IPDM modulation areapplied in the summing technique. FIG. 8(a) shows the signals X_(a) (t),X_(b) (t) and D(t). The frequencies of X_(a) (t), X_(b) (t), the inputsignals to be added, are significantly lower than that of D(t), thetriangle dither signal. For simplicity, since X_(a) (t), X_(b) (t) areslowly-varying compared to D(t), they are shown as straight lines overthe period of D(t). The IPDM signal for each signal X_(a) (t), X_(b) (t)is constructed by computing the times at which each of the signals X_(a)(t), X_(b) (t) intercept D(t). The individual IPDM signals are shown assignal Y[X_(a) (t)] and Y[X_(b) (t)] in FIGS. 8b and 8c, respectively.

As seen earlier in the description of IPDM modulation, the interceptequations depend on the slope of the triangle signal D(t) during each1/2 dither period. If the slope of the triangle is positive, using asimple geometric relationship, and assuming X(t) to be linear over adither time period, the time τ' of the intercept point with the dithersignal D(t) is ##EQU1## If two input signals X_(a) (t) and X_(b) (t) areindividually modulated (see FIGS. 8(b) and (c)) the positive slopeswitch points for the respective signals are ##EQU2## The switch pointof an IPDM waveform (FIG. 8(d)) that results from the linear sum ofX_(a) (t) and X_(b) (t) is, similarly, (see FIG. 8(a)) ##EQU3## X_(a)(t) and X_(b) (t) are two signals that drive two separate modulators inparallel to provide the IPDM waveform of FIGS. 8(b) and 8(c),respectively. The time intercepts τ_(a) ' and τ_(b) ' are, therefore,definable quantities. They are obtained from individual modulatoroutputs. From this information, a time intercept (τ_(a+b')) equivalentto that of the linear sum of X_(a) (t) and X_(b) (t) is obtained. Toreach this end, consider the following relationship between thequantities ##EQU4## By making use of the preceding four equations, thefollowing equation for k is obtained

    k=(τ.sub.b' -(T/4))/τ.sub.b'                       (12)

Thus, substituting equation 12 into 11 ##EQU5##

The triangle waveform (the dither signal) changes from a positive slopeto negative slope each T/2 sec. Over a negative slope region, theintercept equation is derived in a manner similar to that discussed forthe positive slope. The switch point for a single input X(t) is ##EQU6##Although the time of intercept equation differs, the final additionrelationship remains the same as for the positive slope intercept case.That is, ##EQU7## The generalized IPDM addition equation is In IPDMclock counts equation 16A is rewritten as

    N.sub.a+b =N.sub.a +N.sub.b -T.sub.N /4                    (16B)

Where T_(N) is the maximum number of clock counts in the period of thetriangular signal.

Referring now to FIG. 9, a block diagram of an IPDM adder modulator 100,both N_(a) and N_(b) are available as numerical quantities fromindividual IPDM processors 35 operating on the signals X_(a) (t) andX_(b) (t), respectively. The physical two-state waveforms of FIGS. 8(b)and 8(c) themselves are not needed to generate the new two-statewaveform of their linear sum shown in FIG. 8(d). N_(a) and N_(b) are theoutputs, respectively, of respective IPDM processors 35. The outputs,N_(a) and N_(b), are obtained during a T/2 interval of D(t) and equation16B is then computed by IPDM adder 86. The numerical values of N_(a),N_(b) and T_(N) /4 are summed in adder 101 to provide (N_(a) +N_(b)-T_(N) /4) on line 391 to counter 39 which generates a pulse when thecount provided by adder 101 at a rate F' is reached. The counter 39clock frequency, F', (17.92 MHz) is such that a maximum count is reachedin time ≦T/2. The output pulse of counter 39 produced when the countprovided on line 391 is reached changes the output state of switch 41where the output of the switch Y(t)=+G or -G depending upon the sign ofm', (minus or plus, respectively) that is provided by register 36 forthe reason given in the description of the circuit of FIG. 3.

Thus, a time intercept τ_(a+b) defines the switch point instead of τ_(a)or τ_(b) separately. τ_(a+b) cannot exceed T/2, nor can it be negative.If such a condition exists, the switch time is not defined. The factthat the τ_(a+b) exceeds T/2 or is negative yields a count N_(a+b) thatis greater than T_(N) /2 or negative. These occurrences warn that thesummed signal "overmodulates" (overdrives) the processor.

FIG. 10 is an implementation of an IPDM adder modulator by either theone or two term MacLaurin IPDM processor 35' or 35" shown in FIGS. 4 and5. The IPDM adder circuit 110 of FIG. 10 is shown with input signalsX_(a) (t), X_(b) (t) applied to processors 35. In accordance with theearlier presentation of the feedback circuit of FIG. 7, the input signal81 and the feedback signal 89 correspond to the signals X_(a) (t), X_(b)(t) of FIG. 10, respectively. The processors 35 typically may beprocessors 35' of FIG. 4 or processors 35" of FIG. 5 for a one or twoterm approximation of intercept time τ, respectively. The eight-bitbinary number from each processor 35 are provided as inputs to a binarysummer 112. Another input, a seven-bit digital number plus a positivesign bit representing the value of T/4 (≈128 decimal) in clock counts,is provided from register 115 as a negative input of summer 112. Theoutput of summer 112 is an eight-bit binary number (<256 decimal) whichis provided as an input to counter 39 by a sync pulse at a 2F rate fromsource 56. Counter 39 is clocked at the frequency F' (17.92 MHz) toprovide a pulse output at a time τ which corresponds to the summed[X_(a) (t)+X_(b) (t)] intercept time with D(t) as shown in FIG. 8(a).The two state switch 41 changes state at each pulse output of counter 39with the state +G or -G of Y(t) being determined by the sign of m' online 421 provided to switch 41 from a processor 35.

Multiplication in the IPDM Domain

The linearity of interpolation pulse duration modulation over aspecified dynamic range depends on the ratio F/F_(s) of two quantities,the digitizing frequency F relative to the input signal frequency F_(s),F/F_(s). As this ratio increases, the linearity improves. Consequently,the lower the frequency of the input signal and the higher thedigitizing frequency, the better the performance.

Increased bandwidth requirements bring about a lowering of thedigitizing frequency to signal frequency ratio, F/F_(s). Apseudo-modulation scheme has been devised to compensate for thedeterioration in signal linearity for low ratios of F/F_(s). The processinvolves the multiplication of two IPDM signals for which, individually,the relationship F/F_(s) is satisfied. Low frequency information in theresulting IPDM waveform represents the product of the low frequencycomponents within the respective input signals. An input signal thus isable to be modulated and frequency shifted to produce a higher frequencyIPDM waveform. Signal linearity would have deteriorated if thistechnique was not used.

FIG. 11 shows the signals X_(a) (t), X_(b) (t) and D(t). The frequenciesof both the low frequency input signals F_(sa), F_(sb), aresignificantly lower than that of D(t), the triangle dither signal. Forsimplicity consider X_(a) (t), X_(b) (t) to be of constant amplitudeover the period of D(t) (a valid assumption since F_(sa) <<F and F_(sb)<<F). The IPDM signal is constructed by considering the times τ', and τ"at which the signals X_(a) (t), X_(b) (t) intersect D(t). The time atwhich each of the two waveforms intersect D(t) is computed relative tothe times at which the triangle signal D(t) changes slope (the apices ofD(t)). As seen earlier (see IPDM addition), over a positive slope regionof the triangle wave the time τ' (the intercept time) is ##EQU8## whereX' is the amplitude of the input signal X(t) at the sample time whichcoincides with the time of the negative peak of D(t). If two inputsignals X_(a) (t) and X_(b) (t) are individually IPDM modulated ##EQU9##The switch point of a PDM waveform that is the result of the product oftwo waveforms X_(a) (t) and X_(b) (t), is ##EQU10## The time delaysτ_(a) ' and τ_(b) ' are deterministic quantities. They are proportionedto clock counts N_(a) and N_(b) from identical IPDM processors 35a and35b, respectively, of FIG. 12 over a period T/2. From this information,a count N_(ab) proportional to a time intercept τ_(ab) ' equivalent tothat of the of X_(a) '(t) and X_(b) '(t) is computed in computer 132.N_(ab) counted by counter 39 at a rate F', relative to the 2F sync pulseis equivalent to τ_(ab) '.

In order to derive the approximate time delay τ_(ab) ', consider thefollowing relationship between the quantities ##EQU11## Substituting thethree equations 18-20 into Eq. 21, assuming A=1, and solving for k##EQU12## Equation 21 is rewritten as ##EQU13## But, ##EQU14## Thus,substituting X_(a) ' and X_(b) ' (equation 24), equation 23 becomes##EQU15##

If equation 25 is negative or if it is greater than T/2, the multipliedsignal "overmodulates" the processor. Therefore, to prevent"overmodulation" the following conditions must be satisfied: X_(A) ≦A,X_(B)≦A where X_(A), X_(B) and A are peak values of X_(a) (t), X_(b)(t), and D(t), respectively.

The dither signal D(t) has a negative slope over the second half periodT/2. The intercept equation during this time period is ##EQU16## Solvingequation 5 for k with the proper negative slope substitutions, ##EQU17##The product equation τ_(ab) " consequently is ##EQU18## The generalizedmultiplication algorithm is ##EQU19## In general, both τ_(a) and τ_(b)are measurable characteristic properties of the individual PDM signals.The IPDM waveforms themselves are not needed to generate the two statewaveform of their product. The digital IPDM processor circuitry 35 ofFIG. 3 permits the recovery of the counts N_(a) and N_(b) beforeindividual waveform generation since N_(a) and N_(b) are available asnumerical outputs of respective intercept processors 35a, 35b of FIG.12. Counts N_(a) and N_(b), that counted at a rate F', are equivalent toτ_(a) and τ_(b), respectively, during each interval T/2 of D(t).Equation 29 is rewritten in clock counts as the following:

    N.sub.ab =±N.sub.a ±N.sub.b ∓(4/T.sub.N)(N.sub.a)(N.sub.b)+T.sub.N /4∓T.sub.N /4                                          (30)

Where T_(N) equals the number of clock counts in the period of thetriangular signal. Using N_(a) and N_(b), equation 30 for m'+ or-,respectively, is computed by arithmetic processor 132 shown in FIG. 13to provide a numerical count N_(ab) to the counter 39. Counter 39operates at a rate F' and, relative to a 2F sync, generates an outputpulse at the time τ_(ab). The output pulse triggers two state switch 41which changes its output state Y(t) in response to the output pulse andthe sign of m' on line 421; (Y(t)=-G when m' is +and vice versa).

The implementation of IPDM multiplication by the IPDM multipliermodulator 140 of FIG. 13 may use processors 35 of the implementations ofFIGS. 3, 4 and 5. Input signals X_(a) (t) and X_(b) (t) are applied toidentical IPDM processors 35a, 35b, (these are equivalent to processor35) which typically may be a one term approximation-type processor 35'of FIG. 4 or a two term approximation-type processor 35" of FIG. 5. Theeight-bit binary number from each processor 35 is provided to "subtract"inputs of summer 142 of processor 132. The N_(a) output of one of theprocessors 35 is applied to a multiplier 143 whose other input is thequantity 4/T_(N) (1/128 =2⁻⁷ decimal) in the form of a binary numberhaving a sign bit and seven bits to the right of the radix point. Theoutput of multiplier 143 is a binary number of a sign bit and eight bits(one bit of which are to the left of the radix point) and is applied onone input to multiplier 144. The other input of multiplier 144 is theeight-bit binary number N_(b) from processor 35. The output ofmultiplier 144 of the sign plus 16 bits placed in register 145 whichretains only the most significant eight bits and provides them to an"add" input of the summer 142. Summer 142 is followed by a sign inverter150 which changes the sign of the summer 142 output as a function of m'(the slope of D(t)). If m' is negative, the output sign of summer 142 isnot changed. If m' is positive, the output sign of summer 142 isinverted. The output of sign inverter 150 is applied as an input tosummer 149. Summer 149 has another gated input signal from gate 147connected to its input. For the positive slope of D(t), (+m'), equation30 requires the addition of the quantity T_(N) /2 for the determinationof the count of the intercept time of the product X_(a) (t)X_(b) (t)with D(t). Therefore, T_(N) /2 (≈256 decimal) is stored in memory 146 asa sign plus eight-bit digital number. The binary number is gated intosummer 149 by gate 147 when m' is positive (positive slope region ofD(t)) but not when m' is negative (negative slope region of D(t)) sinceequation 30 does not contain the term T_(N) /2. The eight-bit output ofsummer 149, N_(ab), is provided to counter 39 which is reset to a newcount from summer 149 every 1/(2F) seconds (corresponding to the timesof the peak values of D(t)). The count, N_(ab), stored in counter 39 iscounted by the clock pulses at an F' rate and provides a pulse outputwhen the stored count is reached. The sequence of output pulses ofcounter 39 changes the output state Y(t) of two-state switch 41 to -Gwhen m' is positive and to +G when m' is negative. The resultingwaveform of Y(t), Y[X_(a) (t)X_(b) (t)], is the IPDM modulation signalcorresponding to the product of X_(a) (t) and X_(b) (t).

Although this invention has been described in terms of operating onanalog input signals X(t) to produce a pulse duration modulated outputwaveform, it is apparent to those skilled in the art that the inputsignals may have their amplitudes in sequential digital representationas a function of time. Thus, sample circuit 31 of FIG. 4 which providesa digital sampled signal output from an input analog signal and henceimplicitly contains an analog-to-digital converter could provide adigital output from a digital input signal without any need for A/Dconversion. FIG. 7 explicitly designates the input signal as eitheranalog or digital, as one example. Also, operations of the circuitry maybe performed in the analog or digital domain according to the desires ofthe person skilled in the art.

All IPDM modulators described herein have a gain G and hence may also becharacterized as IPDM amplifiers. For this reason the terms "modulator"and "amplifier" are used interchangeably throughout the description ofthe invention.

Having described a preferred embodiment of the invention, it will now beapparent to one of skill in the art that other embodiments incorporatingits concept may be used. It is felt, therefore, that this inventionshould not be restricted to the disclosed embodiment, but rather shouldbe limited only by the spirit and scope of the appended claims.

What is claimed is:
 1. An adder for providing a pulse duration modulatedsignal of the sum of a first and second signal comprising:first andsecond input signals; first and second means providing first and secondnumerical values representing the times of intersection of said firstand second input signals, respectively, with a triangular signalgenerated within each of said first and second means; said times ofintersection being measured from each successive peak value of saidtriangular signal; a synchronizing pulse generator for providingsynchronizing pulses at times corresponding to the peak values of saidtriangular signal; a memory means providing a third numerical valueequal to one-quarter the number of units of time corresponding to theperiod of said triangular signal; adding means summing the first andsecond numerical values and subtracting therefrom said third numericalvalue to provide a fourth numerical value output; a counter responsiveto each said synchronizing pulses to input to said counter the fourthnumerical value provided by said adding means; a source of clock pulsesof higher frequency than said synchronizing pulses providing pulses tosaid counter; said counter providing an output pulse each time that thecount provided by said fourth numerical value is counted by said clockpulses; and a two-state switch responsive to the output pulses of saidcounter to provide a change in the output state of said switch at eachoccurrence of said output pulses.
 2. The adder of claim 1 comprising inaddition:means determining the sign of the slope of said triangularsignal at said successive times of intersection of said first and secondsignals with said triangular signal; and said determining meansproviding said sign to said two-state switch to determine the state ofsaid output state in accordance with said sign.
 3. An adder forproviding a pulse duration modulated signal representation of the sum offirst and second input signals comprising:first and second interpolationpulse duration processors having said first and second input signalsapplied as inputs, respectively; each of said processors sampling itsinput signal and determining the slope of said input signal andcomputing the time interval between said sample time and the time ofintersection of said input signal and a triangular signal generatedwithin said modulator, said time intervals being measured with respectto the successive peak amplitudes of said triangular signal; each ofsaid processors providing at its output a numerical value representingsaid time interval; said time intervals being provided at the output ofeach processor as a first and second number, respectively; a memorymeans for providing a third number equal to one-fourth the numberrepresenting the period of said triangular signal; means for adding saidfirst and second numbers and subtracting said third number to provide afourth number; a counter responsive to each said synchronizing pulses toinput to said counter the fourth number provided by said adding means; asource of clock pulses of higher frequency than said synchronizingpulses providing pulses to said counter; said counter providing anoutput pulse each time that the count input provided by said fourthnumber is counted by said clock pulses; and a two-state switchresponsive to the output pulses of said counter to provide a change inthe output state of said switch at each occurrence of said outputpulses.
 4. The adder of claim 3 comprising in addition: meansdetermining the sign of the slope of said triangular signal at saidsuccessive times of intersection of said first and second signals withsaid triangular signal; andsaid determining means providing said sign tosaid two-state switch to determine the state of said output state inaccordance with said sign.
 5. An adder circuit for providing a pulseduration modulated waveform of the sum of a first and second inputsignal comprising:means for providing synchronizing pulses at a firstfrequency; means for sampling each of said input signals in response tosaid synchronizing pulses at said first frequency to provide for each asuccession of sampled signals; means for storing each sampled signaluntil the next of each succession of sampled signals is provided by saidsampling means in response to said synchronizing pulses; arithmeticprocessing means for computing a first and second number for each ofsaid sampled input signals corresponding to the time measured from eachof said synchronizing pulses to the time of intersection of a straightline linearly interpolated between each sampled signal and itssuccessive stored sample and a straight line between adjacent peaks of atriangular wave generated within said computing means, the peak valuesof said triangular wave occurring at said synchronizing pulse times;means for providing a third number equal to one-quarter of the numbercorresponding to the period of the triangular signal numbers; means foradding said first and second numbers and subtracting said third numberto provide a fourth number; a counter responsive to each saidsynchronizing pulses to input to said counter the fourth number providedby said adding means; a source of clock pulses of higher frequency thansaid synchronizing pulses providing pulses to said counter; said counterproviding an output pulse each time that the count input provided bysaid fourth number is counted by said clock pulses; and a two-stateswitch responsive to the output pulses of said counter to provide achange in the output state of said switch at each occurrence of saidoutput pulses.
 6. The adder of claim 5 comprising in addition:meansdetermining the sign of the slope of said triangular wave at saidsuccessive times of intersection of said linearly interpolated firstsampled signal with said triangular wave; and said determining meansproviding said sign to said two-state switch to determine the state ofsaid output state in accordance with said sign.
 7. An adder circuit forproviding a pulse duration modulated signal of the sum of a first andsecond signal comprising:a first and a second input signal; means forproviding synchronizing pulses at a first frequency; means for samplingsaid first and second input signals in response to said synchronizingpulses to provide successions of sampled first and second signals "b";means for storing each sampled signal until the next of each of saidsuccession of sampled signals is provided by said sampling means inresponse to said synchronizing pulses; means for storing the positiveand negative peak values "b'" and slope values "m'" of a triangulardither signal; means for switching the output of said storing means inresponse to said synchronizing pulses to provide a sequence of a pair ofsaid positive peak value and said negative slope value alternating witha pair of said negative peak value and said positive slope value; anarithmetic processor responsive to said succession of said pairs ofvalues from said switching means and to pairs of one of said successionof sampled signals and one of said succession of stored sampled signalsto compute the slopes "m" of said first and second sampled signals andto compute time t values according to the equation t=(b'- b)/(m - m')for each one of said succession of sampled first and second signals; amemory means for providing a third number equal to one-half the periodof said synchronizing pulses; means for adding said first and secondnumbers and subtracting said third number to provide a fourth number; acounter responsive to each said synchronizing pulses to input to saidcounter the fourth number provided by said adding means; a source ofclock pulses of higher frequency than said synchronizing pulsesproviding pulses to said counter; said counter providing an output pulseeach time that the count input provided by said fourth number is countedby said clock pulses; a two-state switch responsive to the output pulsesof said counter to provide a change in the output state of said switchat each occurrence of said output pulses; a counter set by saidsynchronizing pulse to a number corresponding to the value of time tprovided by said processor; a source of clock pulses of higher frequencythan said synchronizing frequency providing clock pulses to saidcounter; said counter providing an output pulse when the value of numberprovided by the processor is reached; and a two-state switch responsiveto the output pulse of said counter to provide a change in the outputstate of said switch at each occurrence of said output pulse.
 8. Theadder of claim 7 comprising in addition:said means for storing alsoprovides the signs of the slope values "m'" to said two-state switch todetermine the state of said output state in accordance with said signs.9. An adder circuit for providing a pulse duration modulated signal ofthe sum of a first and second signal comprising:first and second inputsignals; first and second interpolation pulse duration processorsconnected to said first and second input signals, respectively; each ofsaid interpolation pulse duration processors comprising: an input signalbeing one of said first and second input signals; means for providing asuccession of synchronizing pulses; means for sampling said input signalin response to said synchronizing pulses to provide a succession ofsampled values of said signal; a summing circuit; means for alternatelyswitching said sampled signal values to the positive and negative inputsof said summing circuit in response to said synchronizing pulses; amemory for providing a number having a value at least as great as thevalues of said sampled signal applied to a positive input of saidsumming circuit; a register storing the output of said summing circuitin response to each said synchronizing pulse; said first and secondinterpolation pulse duration processor registers providing a first andsecond number; an adder circuit for providing a pulse duration modulatedwaveform of the sum of a first and second input signal comprising: meansfor providing synchronizing pulses at a first frequency; means forsampling each of said input signals in response to said synchronizingpulses at said first frequency to provide for each a succession ofsampled signals; means for storing each sampled signal until the next ofeach succession of sampled signals is provided by said sampling means inresponse to said synchronizing pulses; arithmetic processing means forcomputing a first and second number for each of said sampled inputsignals corresponding to the time measured from each of saidsynchronizing pulses to the time of intersection of a straight linelinearly interpolated between each sampled signal and its successivestored sample and a straight line between adjacent peaks of a triangularwave generated within said computing means, the peak values of saidtriangular wave occurring at said synchronizing pulse times; means forproviding a third number equal to one-half the maximum attainable valueof said first or second numbers; means for adding said first and secondnumbers and subtracting said third number to provide a fourth number; acounter responsive to each said synchronizing pulses to input to saidcounter the fourth number provided by said adding means; a source ofclock pulses of higher frequency than said synchronizing pulsesproviding pulses to said counter; said counter providing an output pulseeach time that the count input provided by said fourth number is countedby said clock pulses; and a two-state switch responsive to the outputpulses of said counter to provide a change in the output state of saidswitch at each occurrence of said output pulses.
 10. The circuit ofclaim 9 comprising in addition:said switch providing a sign signalindicative of the position of said switch to said two-state switch; andsaid sign signal controlling the polarity of the output state of saidswitch in accordance with the polarity of said sign.
 11. An addercircuit for providing a pulse duration modulated signal of the sum of afirst and second signal comprising:first and second input signals; firstand second interpolation pulse duration processors connected to saidfirst and second input signals, respectively; each of said interpolationpulse duration processors comprising: an input signal being one of saidfirst and second input signals; means for providing a succession ofsynchronizing pulses; means for sampling said input signal in responseto said pulses to provide a succession of sample values of said signal;means for delaying said sampled signals by the period of said pulses toprovide delayed sampled signals; a first register containing a firstnumber responsive to said pulses to provide an output of said firstnumber with a positive or negative polarity which alternates with eachof said pulses; first means summing the outputs of said sample means,said delay means, and said first register to provide a first summedoutput signal; a second register containing a second number half thevalue of said first number to provide said second number as one outputsignal with alternating polarity in response to said pulses, said firstand second number output signals being of the same polarity during eachalternation; a second means summing the outputs of said delay means andsaid second register; means multiplying the outputs of said first andsecond summing means; a third register storing the successive outputs ofsaid multiplying means in response to said synchronizing pulses; saidfirst and second interpolation pulse duration processor third registersproviding a first and second number; an adder circuit for providing apulse duration modulated waveform of the sum of a first and second inputsignal comprising: means for providing synchronizing pulses at a firstfrequency; means for sampling each of said input signals in response tosaid synchronizing pulses at said first frequency to provide for each asuccession of sampled signals; means for storing each sampled signaluntil the next of each succession of sampled signals is provided by saidsampling means in response to said synchronizing pulses; arithmeticprocessing means for computing a first and second number for each ofsaid sampled input signals corresponding to the time measured from eachof said synchronizing pulses to the time of intersection of a straightline linearly interpolated between each sampled signal and itssuccessive stored sample and a straight line between adjacent peaks of atriangular wave generated within said computing means, the peak valuesof said triangular wave occurring at said synchronizing pulse times;means for providing a third number equal to one-half the maximumattainable value of said first or second numbers; means for adding saidfirst and second numbers and subtracting said third number to provide afourth number; a counter responsive to each said synchronizing pulses toinput to said counter the fourth number provided by said adding means; asource of clock pulses of higher frequency than said synchronizingpulses providing pulses to said counter; said counter providing anoutput pulse each time that the count input provided by said fourthnumber is counted by said clock pulses; and a two-state switchresponsive to the output pulses of said counter to provide a change inthe output state of said switch at each occurrence of said outputpulses.
 12. The circuit of claim 11 comprising in addition:said firstregister providing a sign signal in accordance with the polarity of itsoutput first number to said two-state switch; and said sign signalcontrolling the polarity of the output state of said switch inaccordance with the polarity of said sign.